The most common layout for an integrated circuit chip provides for all power and data connections to the chip at a series of metal bonding pads arrayed in a strip adjacent the entire perimeter of the chip. Although this strip typically is rectangular, it is referred to as an “I/O region”, “I/O ring” or “pad ring” of the chip. In addition to the bonding pads, an I/O region typically includes a region radially inward of the bonding pads that includes power and ground buses in a plurality of metal layers and I/O (input/output) circuitry in semiconductor layers below the metal layers. The remainder of the chip that is encircled by an I/O region is referred to as the core.
Integrated circuit chips are designed by combining many subsystems, commonly called blocks or cells. To reduce design costs, different subsystems within a single chip commonly are designs licensed from different third parties. Subsystems licensed from third parties commonly are referred to as IP (intellectual property) cells.
Some types of subsystems require connections external to the chip. For example, a crystal oscillator subsystem requires two connections to the two pins of a crystal. As explained above, external connections typically are made at the perimeter of a chip. Therefore, subsystems that require external connections commonly are designed to be located in an I/O region so that they can connect directly to the bonding pads. Such subsystems commonly are designed to receive their operating power by direct connections to the bonding pads or to the power buses within an I/O region.
In some chip designs, it may be important for a subsystem in an I/O region to receive its operating power from circuitry in the core region of the chip rather than from the power buses or bonding pads in an I/O region. For example, to modulate power consumption by the subsystem, it may be desirable to include, in the core region of the chip a variable voltage regulator that either varies the voltage supplied to the subsystem or switches the voltage off and on. However, subsystems licensed from third parties that are designed to be located in an I/O region typically do not include a connection path for receiving power from the core; they are only designed to receive power from the power buses or bonding pads in an I/O region.
A similar problem may exist for signals other than power signals, such as analog signals or digital data signals. For example, a subsystem designed to be located in an I/O region may include a first signal connection point at which the subsystem inputs or outputs a first signal. The first signal connection point may be connected to a bonding pad in an I/O region so that the bonding pad is designed to be the only means for connecting the first signal connection point to circuitry outside the subsystem. If the subsystem does not include a connection path between the first signal connection point and the core, then a problem exists if it is desired to connect the first signal connection point to circuitry in the core.
Therefore, a need exists for a connection technique to couple operating power or any other signal between the core of a chip and a subsystem in an I/O region that does not include a connection path for such signal from the core.